Heechun Park, Ph.D.

• Eunsol Jeong, Taewhan Kim and Heechun Park, "Eliminating Minimum Implant Area Violations with Design Quality Preservation," IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 31, No. 5, pp. 611-621, 2023

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• Suwan Kim, Sehyeon Chung, Taewhan Kim and Heechun Park, "Tightly Linking 3D via Allocation towards Routing Optimization for Monolithic 3D ICs," ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), 2022

• Eunsol Jeong, Heechun Park and Taewhan Kim, "A Systematic Removal of Minimum Implant Area Violations under Timing Constraint," IEEE/ACM Design, Automation and Test in Europe Conference (DATE), 2022

• Heechun Park and Taewhan Kim, “Speeding-up Neuromorphic Computation for Neural Networks: Structure Optimization Approach,” Integration, the VLSI Journal, Volume 82, pp.104-114, 2022

• Arjun Chaudhuri, Sanmitra Banerjee, Jinwoo Kim, Heechun Park, Bon Woong Ku, Sukeshwar Kannan, Krishnendu Chakrabarty and Sung Kyu Lim, "Built-in self-test and fault localization for inter-layer vias in monolithic 3D ICs", ACM Journal on Emerging Technologies in Computing Systems (JETC), Vol. 18, No. 1, pp. 1-37, 2022

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• Seyoung Kim, Heechun Park and Jaeha Kim, “Safety Verification of AMS Circuits with Piecewise-Linear System Reachability Analysis,” International System-on-Chip Design Conference (ISOCC), 2021

• Heechun Park, Kyungjoon Chang, Jooyeon Jeong, Jaehoon Ahn, Ki‐Seok Chung and Taewhan Kim, “Challenges on DTCO Methodology Towards Deep Submicron Interconnect Technology,” International System-on-Chip Design Conference (ISOCC), 2021

• Eunsol Jeong, Heechun Park, Jooyeon Jeong and Taewhan Kim, “Minimum Implant Area-Aware Threshold Voltage Refinement in Pre-Placement,” IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2021

• Heechun Park, Bon Woong Ku, Kyungwook Chang, Da Eun Shim and Sung Kyu Lim, “Pseudo-3D Physical Design Flow for Monolithic 3D ICs: Comparisons and Enhancements”, ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 26, No. 5, pp. 1-25, 2021.

• Gauthaman Murali, Heechun Park, Eric Qin, Hakki Mert Torun, Majid Ahadi Dolatsara, Madhavan Swaminathan, Tushar Krishna and Sung Kyu Lim, "Clock Delivery Network Design and Analysis for Interposer-based 2.5D Heterogeneous Systems", IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 29, No. 4, pp. 605-616. 2021

• Taehwan Kim, Heechun Park, and Taewhan Kim, "Allocation of Always-On State Retention Storage for Power Gated Circuits - Steady State Driven Approach," IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 29, no. 3, pp. 499-511, 2021

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• Heechun Park, Jinwoo Kim, Venkata Chaitanya Krishna Chekuri, Majid Ahadi Dolatsara, Mohammed Nabeel, Alabi Bojesomo, Satwik Patnaik, Ozgur Sinanoglu, Madhavan Swaminathan, Saibal Mukhopadhyay, Johann Knechtel, and Sung Kyu Lim, "Design Flow for Active Interposer-Based 2.5D ICs and Study of RISC-V Architecture with Secure NoC," IEEE Transactions on Components, Packaging and Manufacturing Technology(TCPMT), Vol. 10, no. 12, pp. 2047-2060, 2020

• Jinwoo Kim, Gauthaman Murali, Heechun Park, Eric Qin, Hyoukjun Kwon, Venkata Chaitanya Krishna Chekuri, Nael Mizanur Rahman, Nihar Dasari, Arvind Singh, Minah Lee, Hakki Mert Torun, Kallol Roy, Madhavan Swaminathan, Saibal Mukhopadhyay, Tushar Krishna, and Sung Kyu Lim, "Architecture, Chip, and Package Co-design Flow for Interposer-based 2.5D Chiplet Integration Enabling Heterogeneous IP Reuse," IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 28, no. 11, pp. 2424-2437, 2020

• Arjun Chaudhuri, Sanmitra Banerjee, Heechun Park, Jinwoo Kim, Gauthaman Murali, Edward Lee, Daehyun Kim, Sung Kyu Lim, Saibal Mukhopadhyay, and Krishnendu Chakrabarty, “Advances in Design and Test of Monolithic 3D ICs,” IEEE Design & Test, Vol. 37, No. 4, pp. 92-100, 2020

• Heechun Park, Bon Woong Ku, Kyungwook Chang, Da Eun Shim, and Sung Kyu Lim, "Pseudo-3D Approaches for Commercial-Grade RTL-to-GDS Tool Flow Targeting Monolithic 3D ICs," ACM International Symposium on Physical Design (ISPD), 2020

• Jinwoo Kim, Heechun Park, Edward Lee, Daehyun Kim, Arjun Chaudhuriy, Sanmitra Banerjeey, Mark Nelsonz, Krishnendu Chakrabartyy, Saibal Mukhopadhyay, and Sung Kyu Lim, "RTL-to-GDS Design Tools for Monolithic 3D ICs Built with Carbon Nanotube Transistors and Resistive Memory," Government Microcircuit Applications and Critical Technonogy Conference (GOMACTech), 2020

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• Heechun Park, Kyungwook Chang, Bon Woong Ku, Jinwoo Kim, Edward Lee, Daehyun Kim, Arjun Chaudhuri, Sanmitra Banerjee, Saibal Mukhopadhyay, Krishnendu Chakrabarty, and Sung Kyu Lim, "RTL-to-GDS Tool Flow and Design-for-Test Solutions for Monolithic 3D ICs," IEEE/ACM Design Automation Conference (DAC), 2019 (Invited Paper)

• Jinwoo Kim, Gauthaman Murali, Heechun Park, Eric Qin, Hyoukjun Kwon, Venkata Chaitanya Krishna Chekuri, Nihar Dasari, Arvind Singh, Minah Lee, Hakki Mert Torun, Kallol Roy, Madhavan Swaminathan, Saibal Mukhopadhyay, Tushar Krishna and Sung Kyu Lim, "Architecture, Chip, and Package Co-design Flow for 2.5D Integration of Reusable IP Chiplets," IEEE/ACM Design Automation Conference (DAC), 2019

• Arjun Chaudhuri, Sanmitra Banerjee, Heechun Park, Bon Woong Ku, Krishnendu Chakrabarty, and Sung Kyu Lim, "Built-in Self-Test for Inter-Layer Vias in Monolithic 3D ICs," IEEE European Test Symposium (ETS), 2019

• Hakki Mert Torun, Nihar Dasari, Arvind Singh, Minah Lee, Jinwoo Kim, Heechun Park, Hyouk Joon Kwon, Eric Qin, Tushar Krishna, Sung Kyu Lim, Saibal Mukhopadhyay, and Madhavan Swaminathan, "Design Space Exploration of Power Delivery in Heterogeneous Integration," Government Microcircuit Application and Critical Technology Conference (GOMACTech), 2019

• Jinwoo Kim, Eric Qin, Heechun Park, Hakki Mert Torun, Mdhavan Swaminathan, Tushar Krishna, and Sung Kyu Lim, "Enabling Heterogeneous IP Reuse with Interposer-based 2.5D ICs and Custom Interface Protocol," Government Microcircuit Application and Critical Technology Conference (GOMACTech), 2019

• Heechun Park and Taewhan Kim, “Hybrid asynchronous circuit generation amenable to conventional EDA flow,” Integration, the VLSI Journal, Vol. 64, pp. 29-39, 2019

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• Heechun Park and Taewhan Kim, “Structure Optimizations of Neuromorphic Computing Architectures for Deep Neural Networks,” Design, Automation and Test in Europe (DATE), 2018

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• Heechun Park and Taewhan Kim, “Synthesizing Asynchronous Circuits Toward Practical Use,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2016

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• Heechun Park and Taewhan Kim, “Synthesis of TSV Fault-Tolerant 3D Clock Trees,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 34, No. 2, pp. 266-279, 2015

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• Heechun Park and Taewhan Kim, “Comprehensive Technique for Designing and Synthesizing TSV Fault-Tolerant 3D Clock Trees,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2013

• Heechun Park and Taewhan Kim, “Fault Coverage and Resource Analysis for Diverse Structures of Clock TSV Fault-Tolerant Units in 3D ICs,” IEEE International SOC Design Conference (ISOCC), 2013